1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Description of the Related Art
Semiconductor devices carrying thereon a combination of a logic region and a capacitor element region require many steps for manufacturing, and hence a reduction in production lead time has been focused on. Conventionally, the actual production is started only after establishing the design of all reticles to be employed, which inevitably prolongs the lead time. On the other hand, in the case of starting the production prior to establishing the design of the reticles, the semiconductor device has to be reworked from start, each time the reticle is modified because of a design change of the device. This naturally leads to an increase in the manufacturing cost.
As an attempt to shorten the lead time, JP-A Laid Open No. 2002-289817 proposes a semiconductor integrated circuit including a gate array section and an intellectual properties (hereinafter, abbreviated as IP) section. In the semiconductor device disclosed in JP-A Laid Open No. 2002-289817, a source and a drain diffusion layers and a gate electrode of a transistor, as well as a part of an interconnect of the respective sections are formed in advance through a front-end wafer process, to be used in common for all products. Such an arrangement reportedly allows reducing a production lead time of a sample product.